In this paper we present a general framework for architectural design of large hierarchical
multiprocessor systems under rapidly changing packaging, processor, and interconnection
technologies. Processor boards with larger area (A) and greater pinouts
are becoming feasible. Board interconnection technology has advanced from only peripheral
connections O(pA) to elastomeric surface connections O(A). As processor
and interconnection technology is growing, there is a varying demand on the interconnection
network of the system. The proposed framework is capable of taking into
account all these changing technologies. Each technology is captured through one or
more parameter(s) which reflects its level of advancement. Depending on a given set of
values of these parameters, the framework guides us to choose the most optimum topology.
The framework is illustrated by considering the design problem of the currently
popular k-ary n-cube cluster-c scalable architecture. These architectures combine the
scalability of k-ary n-cube wormhole-routed networks with the cost-effectiveness of processor
cluster designs. Each cluster consists of c processors interconnected through a
bus/MIN/direct network. Our results indicate that under surface pinout technology an
increase in cluster size(c) is associated with a growth in bisection bandwidth, whereas
in periphery pinout it leads to a fall in bisection bandwidth. For systems supporting
16-bit links, cluster sizes of 2 to 3 processors with 3D/4D k-ary n-cube interconnections
are optimal. Similarly systems with 32-bit links can support larger cluster sizes(c=7,8)
and 3D/4D interconnections.