Switch-based interconnects are used in a number of application domains including parallel
system interconnects, local area networks, and wide area networks. However, very few switches
have been designed that are suitable for more than one of these application domains. Such a switch
must offer both extremely low latency and very high throughput for a variety of different message
sizes. While some architectures with output queuing have been shown to perform extremely well in
terms of throughput, their performance can suffer when used in systems where a significant portion
of the packets are extremely small. On the other hand, architectures with input queuing offer
limited throughput, or require fairly complex and centralized arbitration that increases latency.